Packaging is one of the final steps in the process of manufacturing integrated semiconductor circuit components or chips. In packaging, a fabricated semiconductor chip is mounted in a protective housing. After packaging, the assembled component is subjected to final testing and ultimately then connected into an electronic circuit.
Currently, many semiconductor chips are contained in plastic packages. These packages are provided with reinforced metal leads for electrically connecting the chip to the printed circuit board which contains the circuit in which the chip is to be included. Within the package, one end of each lead is connected to a specific bonding point on the chip, usually by an intermediate lead. The other end of the lead, which extends outside of the package, is attached to a connection on the printing circuit board.
Advances in semiconductor manufacturing technology have made the fabrication of Very Large Scale Integration (VLSI) chips possible. A VLSI chip comprises a large number of individual circuit components that are fabricated together on a single, small chip. VLSI chips are able to perform a large number of electrical functions, and perform them more rapidly, than was previously possible.
To date, it has been difficult to provide suitable packaging for VLSI chips. In part, this is because each chip requires a large number of connections to external circuit elements. Many VLSI chips have over 300 bonding points, each of which must be connected to a lead for connection to external circuit elements.
Another consideration in the use of a VLSI chip is the need to provide common voltages to a number of different locations on the chip. For instance, in a chip that comprises a number of individual C-MOS transistors, such a chip may require a common drain voltage and a common source voltage for the transistor provided by an external power supply. Typically, the drain voltage is positive with respect to a common reference or ground voltage and the source voltage is typically at the same level as the ground voltage.
Normally, common voltages are supplied to the components on the chip by providing sets of leads. Each set of leads carries the same voltage to different bond points on the chip. To date, providing a VLSI chip with a common voltage at a number of locations has been a difficult task. In a VLSI package, the leads which are connected to the chip are spaced closely together. Moreover, some of the leads supply signal voltages that fluctuate rapidly as electronic functions are performed by the chip and the other circuit components This causes the magnetic fields normally developed around these leads to vary which in turn causes inductive currents to flow in adjacent leads. Whenever a sufficiently large inductive current is developed in a common voltage lead, the voltage on the lead changes. This problem may be intensified because in a VLSI chip voltages may fluctuate rapidly. This rapid change also intensifies the development of a magnetic field and the associated inductive current flow. As a result, the voltage supplied to one or more components on the VLSI chip may vary so greatly as to cause the chip to malfunction.
There are prior VLSI chip packages that are designed to minimize the problems associated with the development of inductive current flow. One such package is a multi-layered ceramic package. This package includes layers of conductors separated by layers of dielectric ceramic. A cavity is formed in the ceramic layers and the chip is mounted in the cavity. Wire bonds connect the bond points on the chip to the individual conductors on the top layer of conductors. Individual wire bonds or reinforced metal leads provide an electrical connection to the printed circuit board to which the chip is attached. Selected top-layer conductors, which carry common voltages, are connected to common intermediate-layer conductors. The intermediate-layer conductors function as reference voltage planes which insure that the common voltages supplied through the top-layer conductors attached thereto does not appreciably vary.
However, there are a number of limitations associated with multi-layer ceramic packages. The size of these packages tends to be overly large in order to accommodate the interconnections needed between the conductor layers. Moreover, a ceramic package designed to contain a VLSI chip is expensive to manufacture. In some instances, the cost of the multi-layered ceramic package may significantly exceed the cost of fabricating the chip.
There have also been some attempts at providing packages for semiconductor chips wherein a single lead, bonded to the package, extends out from the package and has an outer lead portion that is used for subsequent bonding to a printed circuit conductor or other circuit elements. These packages have been formed from leads that extend from a section of metal tape. They can be used to provide only a relatively limited number of leads and thus do not provide the number of required interconnections needed for VLSI chips and the like. Moreover, to prevent environmental exposure of the packaged chip, which may cause the chip's degradation and malfunction, the package is often filled with an encapsulation material so as to entirely cover the chip and the leads thereto. The encapsulation is a difficult and time consuming process that adds to the overall expense of packaging the chip. Furthermore, there are some difficulties associated with removing the encapsulating material in order to access the packaged chip.